With of the advent of System-on-Chips (SoC) and Chip-Multiprocessing (CMP), Network-on-Chips (NoC) are becoming more utilized. One design challenge in any NoC is providing adequate destination buffer space for good performance across a wide range of applications with reasonable area overhead and area inefficiency.
Conventional NoC architectures range from ring to mesh topologies. In these topologies, all the destination queues may be physically located at the destination agent. In a mesh topology, each cross-point also contains a small crossbar switch. In addition, buffers need to be provided at each intermediate stop or cross-point.
Implementing a large number of distinct queues leads to a large area overhead and large degree of area inefficiency. Also, since the destination queues are physically located at the destination agent, it is not possible to reconfigure the queues according to the application requirement. In order, to provide adequate performance for a wide range of applications, all the queues have to be sized to the maximum required size even though not all queues need to be maximum sized for any one application. The intermediate buffers and cross-bar switch at each stop or cross-point also consume significant area. There is thus a need for addressing these and/or other issues associated with the prior art.